The present invention relates to a computer system configured by a plurality of computer modules connected to one another through a bus and, more specifically, to a technique effectively applicable to a method and an apparatus configuration of adjusting a bus resource such as a bus clock and an interrupt.
In relation to a method of connecting the computer modules through a bus, a bus technique disclosed in, for example, PC/104 Embedded Consortium “PC/104-Plus Specification Version 2.0” (Non-patent Document 1) is known. Namely, the bus technique is PC/104-Plus in which a plurality of computer modules or input/output modules (hereinafter, “computer modules”) are connected to one another through stacking connectors (hereinafter, “conventional example 1”).
In this conventional example 1, a Peripheral Component Interconnect (PCI) bus disclosed in PCI SIG “PCI Local Bus Specification Rev 2.3” (Non-patent Document 2) is used as a bus protocol, and an electric signal line is compliant with PCI bus specification.
Signals necessary for management and operation of a bus are referred to as “bus resources” in the present specification. Examples of the bus resources include a clock signal for allowing devices connected to the bus to operate synchronously with one another, a bus arbitration (bus request/bus grant) signal for arbitrating an ownership of the bus, a bus interrupt signal for causing one of the devices to notify the other devices of an event, and an IDSEL signal for designating one device during a device configuration.
In the conventional example 1, it is required for one module to manage the bus resources and for the other modules to exclusively connect the bus resources. As such a method, an example of configuring the modules according to physical positions of the modules using switches and jumper wires, etc. is disclosed in the conventional example 1.
Meanwhile, a technique for preparing a plurality of bus arbitration apparatuses for managing bus arbitration signals to enable one of the bus arbitration apparatuses is disclosed in Japanese Patent Laid-Open Publication No. 2000-347991 (Patent Document 1) (hereinafter, “conventional example 2”).
According to the conventional example 2, in data processing apparatuses equal in configuration and each including the bus arbitration apparatus are connected to a backplane on which the bus signals are supplied in advance. Only one of the bus arbitration apparatuses receiving and handling the bus arbitration signal must be activated on a bus system. To attain such a purpose, the conventional example 2 discloses a technique for activating only one among the plurality of bus arbitration apparatuses.